Before you start using Intel® IPP, it is helpful to understand some basic concepts:
Intel® IPP includes two levels of building blocks.
The primitives are abstractions of fundamental operations such as convolution filters or image resize. They are intended to be highly optimized implementations of small performance-critical operations. These are implemented in C and Assembler in "layers" targeting specific Intel architectures (see Dispatching below).
The high level APIs are provided for convenience, since a significant amount of infrastructure is required around the performance-critical sections optimized with primitives. Full source code is available for these samples so they can be altered to fit a variety of scenarios. These samples are starting points, built with the assumption that many of their components (I/O and others) will be replaced if incorporated by developers and put into production. As such, they are not optimized, tested, or supported at the same level as the primitives. Please keep in mind that the media APIs may not fully implement the specs for each codec and splitters/muxers are intended merely as developer tools to facilitate codec evaluation.
The extensive functionality of Intel® IPP is subdivided into several domains. Please refer to the section "Domains" to understand what function domains are, and to the table "Library Dependencies by Domain" to understand what kinds of cross-domain dependencies are introduced.
One of the key features of Intel® IPP is that it provides a single interface to multiple underlying implementations optimized for each generation of Intel hardware. For more information see the section on dispatching in this document, as well as the KB article at Understanding SIMD Optimization Layers and Dispatching in the Intel® IPP 7.1 Library.
Intel® IPP provides three linking models:
Dynamic shared library/DLL
Single-threaded static
Multi-threaded static
Multithreaded static libraries are provided in a separate package available for download from the Intel® Software Development Products Registration Center web site at https://registrationcenter.intel.com/ .
For more information on each of the linking models, see the section on linking models in this document or refer to the KB article Introduction to Linking with the Intel® IPP 7.1 Library available at http://software.intel.com/en-us/articles/introduction-to-linking-with-intel-ipp-71-library.
Internal threading is deprecated and will be removed in a future release. Moving to single threaded IPP functions is highly recommended.
More options for better overall performance and thread control are available when the application handles the threading.
Many of the Intel® IPP functions are internally threaded with OpenMP*. A list is available in the documentation directory in the file ThreadedFunctionsList.txt.
For more information please see the Supporting Multithreaded Applications section in this document.
The following parts of Intel® IPP are distributed in separate packages downloadable from the Related Files section at Intel® Software Development Products Registration Center web site:
IPP GEN Add-on Library for Signal Processing contains the generated signal processing function domain. This domain is deprecated and will be removed in a future release.
IPP Samples contain a wide variety of demos and starting points for IPP development. Some of the samples are high level APIs. Please see the High-level APIs vs. Primitive section above for more information.
UIC and DMIP Binary Samples are pre-compiled sample applications showcasing Unified Image Classes and Deferred Image Mode Image Processing.
IPP Threaded Static Libraries contain the threading (_t) function implementations for use with static linking.
Internal threading is deprecated and will be removed in a future release. Moving to single threaded IPP functions is highly recommended.
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Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 |