Intel® IPP uses multiple function implementations optimized for various central processing units (CPUs). Dispatching refers to detection of your CPU and selecting the corresponding Intel IPP binary path. For example, the ippie9-7.1 shared library in the /redist/intel64/ipp directory contains the image processing libraries optimized for 64-bit applications on AVX-enabled processors such as the Intel® 2nd Generation Core™ processor family.
A single Intel IPP function, for example ippsCopy_8u(), may have many versions, each one optimized to run on a specific Intel® processor with specific architecture, for example, the 64-bit version of this function optimized for the Intel® 2nd Generation Core™ processor is e9_ippsCopy_8u(), and version optimized for 64-bit applications on processors with Intel® SSE4.1 is y8_ippsCopy_8u(). This means that a prefix before the function name determines CPU model. However, during normal operation the dispatcher will determine the best version and a generic function (ippsCopy_8u in this example) can be called.
Intel® IPP is designed to support application development on various Intel architectures. This means that the API definition is common for all processors, while the underlying function implementation takes into account the strengths of each hardware generation.
By providing a single cross-architecture API, Intel® IPP enables you to port features across Intel® processor-based desktop, server, and mobile platforms. You can use your code developed for one processor architecture for many processor generations.
The following table shows processor-specific codes used in Intel IPP:
|
Abbreviation |
Meaning |
|---|---|
|
IA-32 Intel® architecture |
|
|
w7 |
Optimized for processors with Intel® Streaming SIMD Extensions 2 (Intel® SSE2) |
|
v8 |
Optimized for the Intel® Atom™ processor and processors with Intel® Supplemental Streaming SIMD Extensions 3 (SSSE3) |
|
p8 |
Optimized for processors with Intel SSE4.1, SSE4.2, and Intel® Advanced Encryption Standard New Instructions (Intel® AES-NI) |
|
g9 |
Optimized for processors with Intel AVX and AES-NI |
|
h9 |
Optimized for processors with Intel® Advanced Vector Extensions (Intel® AVX2) |
|
Intel® 64 architecture |
|
|
m7 |
Optimized for processors with Intel SSE3 |
|
u8 |
Optimized for the Intel® Atom™ processor and 64-bit applications on processors with SSSE3 |
|
y8 |
Optimized for 64-bit applications on processors with Intel SSE4.1 |
|
e9 |
Optimized for processors with Intel AVX instruction set |
|
l9 |
Optimized for processors with Intel AVX2 |
|
Intel's compilers may or may not optimize to the same degree for non-Intel microprocessors for optimizations that are not unique to Intel microprocessors. These optimizations include SSE2, SSE3, and SSSE3 instruction sets and other optimizations. Intel does not guarantee the availability, functionality, or effectiveness of any optimization on microprocessors not manufactured by Intel. Microprocessor-dependent optimizations in this product are intended for use with Intel microprocessors. Certain optimizations not specific to Intel microarchitecture are reserved for Intel microprocessors. Please refer to the applicable product User and Reference Guides for more information regarding the specific instruction sets covered by this notice. Notice revision #20110804 |