Code Generation Options
- arch
Tells the compiler which features it may target, including which instruction sets it may generate.
- ax, Qax
Tells the compiler to generate multiple, feature-specific auto-dispatch code paths for Intel® processors if there is a performance benefit.
- EH
Specifies the model of exception handling to be performed.
- fasynchronous-unwind-tables
Determines whether unwind information is precise at an instruction boundary or at a call boundary.
- fexceptions
Enables exception handling table generation.
- fomit-frame-pointer, Oy
Determines whether EBP is used as a general-purpose register in optimizations.
- Gd
Makes __cdecl the default calling convention.
- Gr
Makes __fastcall the default calling convention.
- GR
Enables or disables C++ Run Time Type Information (RTTI).
- Gz
Makes __stdcall the default calling convention.
- hotpatch
Tells the compiler to prepare a routine for hotpatching.
- m
Tells the compiler which features it may target, including which instruction sets it may generate.
- m32, m64
Tells the compiler to generate code for a specific architecture.
- march
Tells the compiler to generate code for processors that support certain features.
- masm
Tells the compiler to generate the assembler output file using a selected dialect.
- minstruction, Qinstruction
Determines whether MOVBE instructions are generated for Intel processors.
- mtune
Performs optimizations for specific processors.
- Qcxx-features
Enables standard C++ features without disabling Microsoft features.
- Qpatchable-addresses
Tells the compiler to generate code such that references to statically assigned addresses can be patched.
- Qsafeseh
Registers exception handlers for safe exception handling.
- regcall, Qregcall
Tells the compiler that the __regcall calling convention should be used for functions that do not directly specify a calling convention.
- x, Qx
Tells the compiler which processor features it may target, including which instruction sets and optimizations it may generate.
- xHost, QxHost
Tells the compiler to generate instructions for the highest instruction set available on the compilation host processor.